Dave Fick is a full-stack computer engineer, with significant experience in software engineering, computer architecture, digital integration, and full-custom design for analog, digital, and flash circuits. He works towards first-pass success through process-driven methodology which unites all layers of the system. He received his PhD in Computer Science and Engineering from the University of Michigan.

He is currently CTO/Founder at Mythic.

He is an alumnus of the University of Michigan, Ann Arbor. There he worked with Professors Dennis Sylvester and David Blaauw of the Michigan Integrated Circuits Lab (MICL).

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S. Skrzyniarz, L. Fick, J. Shah, Y. Kim, D. Sylvester, D. Blaauw, D. Fick, and M. B. Henry. A 36.8 2b-TOPS/W Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65nm LP CMOS. ISSCC, 2016.

L. Fick, D. Fick, M. Alioto, D. Blaauw, and D. Sylvester. A 346μm² VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes 28nm CMOS. JSSC, 2014.

I. Kwon, S. Kim, D. Fick, M. Kim, Y. Chen, and D. Sylvester. Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails. JSSC, 2014.

D. Fick, G. Kim, A. Wang, D. Blaauw, and D. Sylvester. Mixed-Signal Stochastic Computation Demonstrated in an Image Sensor with Integrated 2D Edge Detection and Noise Filtering. Proc. CICC, 2014.

K. Yang, D. Fick, M. B. Henry, D. Blaauw, and D. Sylvester. A 23Mb/s, 23pJ/bit Fully-Synthesized True Random Number Generator in 28nm and 65nm CMOS. Proc. ISSCC, 2014.

L. Freyman, D. Fick, D. Blaauw, D. Sylvester, and M. Alioto. A 346μm² Reference-Free Sensor Interface for Highly Constrained Microsystems in 28nm CMOS. Proc. A-SSCC, 2013.

N. Pinckney, K. Sewell, R. G. Dreslinski, D. Fick, D. Sylvester, T. Mudge, and D. Blaauw. Limits of Parallelism and Boosting in Dim Silicon. IEEE Micro, 2013.

R. G. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. Communications of the ACM, Nov. 2013.

B. Giridhar, M. Fojtik, D. Fick, D. Sylvester, and D. Blaauw. Pulse Amplification Based Dynamic Synchronizers with Metastability Measurement using Capacitance De-rating. Proc. CICC, 2013.

H. Ghaed, G. Chen, R. Haque, M. Wieckowski, Y. Kim, G. Kim, Y. Lee, I. Lee, D. Fick, D. Kim, M. Seok, K. Wise, D. Blaauw, D. Sylvester. Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor. TCAS-I, 2013. [IEEE]

R. G. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Centip3De: A 64-Core, 3D Stacked, Near-Threshold System. IEEE Micro, 2013.

S. Kim, I. Kwon, D. Fick, M. Kim, Y. Chen, and D. Sylvester. Razor-Lite: A Side-Channel Error-Detection Register for Timing-Margin Recovery in 45nm SOI CMOS. Proc. ISSCC, 2013.

D. Fick, R. G. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Centip3De: A Cluster-Based NTC Architecture with 64 ARM Cortex-M3 Cores in 3D Stacked 130nm CMOS. JSSC, 2013. [IEEE]

M. Fojtik, D. Kim, G. Chen, Y. Lin, D. Fick, J. Park, M. Seok, M. Chen, Z. Foo, D. Blaauw, and D. Sylvester. A Millimeter-scale Energy-autonomous Sensor System with Stacked Battery and Solar Cells. JSSC, 2013.

M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. Harris, D. Blaauw, and D. Sylvester. Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45nm CMOS Using Architecturally Independent Error Detection and Correction. JSSC, 2013. [IEEE]

R. G. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Centip3De: A 64-Core, 3D Stacked, Near-Threshold System. Proc. HOTCHIPS, 2012. [IEEE] [slides]

N. Pinckney, K. Sewell, R. G. Dreslinski, D. Fick, D. Sylvester, T. Mudge, and D. Blaauw. Assessing the Performance Limits of Parallelized Near-Threshold Computing. Proc. DAC, 2012. [PDF]

A. DeOrio, D. Fick, V. Bertacco, D. Sylvester, D. Blaauw, J. Hu, and G. Chen. A Reliable Routing Architecture and Algorithm for NoCs. TCAD, Volume 31, Issue 5, May 2012. [PDF]

D. Fick, R. G. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Centip3De: A 3930 DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores. Proc. ISSCC, 2012. [PDF] [slides] [TheRegister]

M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. Harris, D. Blaauw, and D. Sylvester. Bubble Razor: An Architecture Independent Approach to Timing Error Detection and Correction. Proc. ISSCC, 2012. [PDF] [slides]

B. Giridhar, D. Fick, M. Fojtik, S. Satpathy, D. Bull, D. Sylvester, D. Blaauw. Adaptive Robustness Tuning for High Performance Domino Logic. Proc. VLSI Symp., 2011. [PDF] [slides]

G. Chen, H. Ghaed, R. Haque, M. Wieckowski, Y. Kim, G. Kim, D. Fick, D. Kim, M. Seok, K. Wise, D. Blaauw, D. Sylvester. A 1 Cubic Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor. Proc. ISSCC, 2011. [PDF] [slides]

D. Fick, N. Liu, Z. Foo, M. Fojtik, J. Seo, D. Sylvester, and D. Blaauw. In Situ Delay Slack Monitor for High-Performance Processors using an All-Digital, Self-Calibrating 5ps Resolution Time-to-Digital Converter. Proc. ISSCC, 2010. [PDF] [slides] [IEEE]

G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M. Chen, Z. Foo, D. Sylvester, and D. Blaauw. A Millimeter-Scale Nearly-Perpetual Sensor System with Stacked Battery and Solar Cells. Proc. ISSCC, 2010. [PDF] [slides] [IEEE]

D. Fick, A. DeOrio, J. Hu, V. Bertacco, D. Blaauw, and D. Sylvester. Vicis: A Reliable Network for Unreliable Silicon. Proc. DAC, 2009. [PDF] [IEEE] [ACM]

R. G. Dreslinski, D. Fick, D. Blaauw, D. Sylvester, and T. Mudge. Reconfiguarable Multicore Server Processors for Low Power Operation. Proc. SAMOS, 2009. [ACM]

D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw. A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs. Proc. DATE, 2009. [PDF] [IEEE]

D. F. Lemmerhirt, D. A. Fick, and K. D. Wise. An autonomous Microsystem for Environmental and Biological Data Gathering. Digest Int. Conf. on Solid-State Sensors, Actuators, and Microsystems, 2005. [IEEE]

D. Sylvester, D. Blaauw, D. Fick, Y. Lee, K. Yang, M. B. Henry, True Random Number Generator, patent filed.

B. Giridhar, M. Fojtik, D. Fick, D. Sylvester, and D. Blaauw, Dynamic Circuitry Using Pulse Amplification to Reduce Metastability, patent filed.

D. Fick, R. G. Dreslinski, T. Mudge, D. Blaauw, and D. Sylvester, Vertical interconnect patterns in multi-layer integrated circuits, patent granted. [link]

M. Fojtik, D. Sylvester, D. Blaauw, and D. Fick, Stalling synchronisation circuits in response to a late data signal, patent granted. [link]

D. Blaauw, D. Sylvester, D. Fick, S. Biles, M. Wieckowski, S. Hanson, and G. Chen, Operating parameter control of an apparatus for processing data, patent granted. [link]

D. Fick, R. G. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Design and Implementation of Centip3De, a 7-layer Many-Core System. 2011 ISSCC/DAC Student Design Contest Winner. [article]

AMD Design Contest, 1st Place, 2006. [article]

Mythic

CTO/Founder

August 2012 - Present

With no compromises on performance, Mythic makes it easy to add transformative AI to any device.

IBM

VLSI Researcher

May 2010 - August 2010

Analyzed power distribution for 3D integrated systems through C4 and through-silicon via (TSV) structures. Developed tools to accelerate analysis through parametric sweeps of TSV placement, density, and design.

NVIDIA

Computer Architect

January 2007 - August 2007

Worked on architectural model and bringup driver teams for the GPU architecture group. Extensive experience with C++, hardware modeling, and validation. Wrote OpenGL extension specifications, implemented driver support, implemented architectural model support, and wrote OpenGL-based verification tests.

Intel

Design Engineer

May 2006 - August 2006

Worked with L0 Data Cache design team for the 45nm Nehalem project. Responsible for a functional block through quality checks and assisted with two others. Also performed interconnect analysis for section routing. Fixed delay, slope, structural and other violations in functional units using Cadence and the custom tool flows. Created repeater solutions for hundreds of nets in the section and made recommendations to reduce congested areas. Used PERL for some analysis.

Advanced Micro Devices

Software Engineer

May 2005 - August 2005

Ported four applications from Windows to Linux and created a new cross-platform application. Applications used the Qt GUI system, interacted with the processor MSRs and operating system, and were submitted to QA.

Advanced Micro Devices

Board Design Engineer

January 2005 - April 2005

Assisted with schematic design and layout checking for a burn-in testing and validation board. Also responsible for the creation of a new design, a cooling solution controller board, featuring a 100 pin CPLD, MOSFETs, BJTs, Power Supplies; over 400 components total.

Ph.D. Thesis: Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits. [link]
Ph.D. Co-advisors Professors Dennis Sylvester and David Blaauw
Ph.D. Computer Science and Engineering, 2012, University of Michigan, Ann Arbor
M.S.E. Computer Science and Engineering, 2009, University of Michigan, Ann Arbor
B.S.E. Computer Engineering, 2006, Magna Cum Laude, University of Michigan, Ann Arbor

Relevant Coursework:

	VLSI Design I VLSI Design II Advanced High Performance VLSI Monolithic Amplifier Circuits	Computer Architecture Microarchitecture Parallel Computer Architecture Enterprise Computer Architecture	Data Structures & Algorithms Intro Operating Systems Intro Artificial Intelligence Parallel Computing Interactive Computer Graphics Neural Networks for Machine Learning (Coursea)
	Digital Integrated Circuits Intro Semiconductor Devices Digital Integrated Technologies	Design of Microprocessor Based Systems Embedded Control Systems Digital System Testing

VLSI Design I Project:
Mixed Full Custom Design and Synthesis 16-bit RISC Core, 5-Stage Pipeline, Banked Memory, Pulsed-Latch Registers, Kogge-Stone Adder, Booth-Recoded Wallace Tree Multiplier. 348 MHz in 0.25um - Class record - [article]

Computer Architecture Project:
Verilog 64-bit RISC Core, PRF/ROB Out-of-Order Operation, 2x Superscalar, Forwarding Speculative Load-Store Queue, Non-Blocking Caches, Victim Cache, Quick Branch Resolution

Serial Communicator - I wrote this Deperlify based chip I/O for tapeouts at Michigan, and released it on opencores.org.

Wikipedia - I contribute to some VLSI related articles here.